A scheme to improve the stability and accuracy of power hardware-in-the-loop simulation

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Abstract

Power hardware-in-the-loop (PHIL) is a state-of-the-art simulation technique that combines real-time digital simulation and hardware experiments into a closed-loop testing environment. The transportation delay or communication latency impacts the stability and accuracy of PHIL simulations. In this paper, for the purpose of synchronizing the PHIL output signal and promoting both the stability and accuracy of PHIL simulation, a hybrid compensation scheme is proposed to compensate for the time delay in the PHIL configuration. A model-based compensator is implemented to shift the time delay out of the PHIL closed-loop to enhance PHIL stability. A time delay compensation model and its equivalent inverse model are employed in the PHIL closed-loop to compensate for the time delay. A phase lead compensator and digital linear-phase frequency sampling filter (FSF) are candidate compensation models to compensate for the time delay and reshape the phase curve on a harmonic-by-harmonic basis. Simulations are made to validate the effectiveness of the compensation scheme.
Original languageEnglish
Title of host publicationIECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society
Place of PublicationPiscataway, N.J.
PublisherIEEE
Pages5027-5032
Number of pages6
ISBN (Electronic)978-1-7281-5414-5
DOIs
Publication statusPublished - 18 Nov 2020
EventIECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society - Singapore, Singapore, Singapore
Duration: 18 Oct 202021 Oct 2020
https://www.iecon2020.org/

Conference

ConferenceIECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society
CountrySingapore
CitySingapore
Period18/10/2021/10/20
Internet address

Keywords

  • power hardware-in-the-loop (PHIL)
  • model-based compensator
  • time delay compensation
  • stability and accuracy
  • frequency sampling filter

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