A new control method for the power interface in power hardware-in-the-loop simulation to compensate for the time delay

Efren Guillo Sansano; Andrew Roscoe; Catherine Jones; Graeme Burt

doi:10.1109/UPEC.2014.6934618

A new control method for the power interface in power hardware-in-the-loop simulation to compensate for the time delay

Efren Guillo Sansano, Andrew Roscoe, Catherine Jones, Graeme Burt

Electronic And Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution book

29 Citations (Scopus)

138 Downloads (Pure)

Abstract

In an attempt to create a new control method for the power interface in PHIL simulations, a simulated PHIL simulation is carried out where the simulation and hardware part are modelled in MATLAB/Simulink along with the new control method. This power interface control is proposed to achieve high accuracy in PHIL simulation with closed-loop control for aerospace, marine or micro grid applications. Rather than analyzing the Real Time Simulator (RTS) data and controlling the interface using time-domain resonant controllers, the RTS data will be analyzed and controlled at the interface in the frequency domain, on a harmonic-by-harmonic and phase-by-phase basis. This should allow the RTS time delay to be compensated accurately, and removes the requirement to include additional components to compensate for the simulation delay into the simulated power system as it is not appropriate for power systems which have short transmission lines. This is extremely relevant for marine and micro grid scenarios where such inductive components may not be present.

Original language	English
Title of host publication	2014 49th International Universities Power Engineering Conference (UPEC)
Publisher	IEEE
Number of pages	5
ISBN (Print)	978-1-4799-6556-4
DOIs	https://doi.org/10.1109/UPEC.2014.6934618
Publication status	Published - Sept 2014
Event	49th International Universities Power Engineering Conference, UPEC 2014 - Cluj-Napoca, Romania Duration: 2 Sept 2014 → 5 Sept 2014

Conference

Conference	49th International Universities Power Engineering Conference, UPEC 2014
Country/Territory	Romania
City	Cluj-Napoca
Period	2/09/14 → 5/09/14

Keywords

interface algorithm
real-time systems
simulation accuracy
simulation time delay

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/UPEC.2014.6934618

C_2014_UPEC_Guillo-Sansano_PHIL_PostPrintAccepted author manuscript, 782 KB

Cite this

@inproceedings{319c14a9bc124d65938f702c1cedd2f4,

title = "A new control method for the power interface in power hardware-in-the-loop simulation to compensate for the time delay",

abstract = "In an attempt to create a new control method for the power interface in PHIL simulations, a simulated PHIL simulation is carried out where the simulation and hardware part are modelled in MATLAB/Simulink along with the new control method. This power interface control is proposed to achieve high accuracy in PHIL simulation with closed-loop control for aerospace, marine or micro grid applications. Rather than analyzing the Real Time Simulator (RTS) data and controlling the interface using time-domain resonant controllers, the RTS data will be analyzed and controlled at the interface in the frequency domain, on a harmonic-by-harmonic and phase-by-phase basis. This should allow the RTS time delay to be compensated accurately, and removes the requirement to include additional components to compensate for the simulation delay into the simulated power system as it is not appropriate for power systems which have short transmission lines. This is extremely relevant for marine and micro grid scenarios where such inductive components may not be present.",

keywords = "interface algorithm, real-time systems, simulation accuracy, simulation time delay",

author = "{Guillo Sansano}, Efren and Andrew Roscoe and Catherine Jones and Graeme Burt",

year = "2014",

month = sep,

doi = "10.1109/UPEC.2014.6934618",

language = "English",

isbn = "978-1-4799-6556-4 ",

booktitle = "2014 49th International Universities Power Engineering Conference (UPEC)",

publisher = "IEEE",

note = "49th International Universities Power Engineering Conference, UPEC 2014 ; Conference date: 02-09-2014 Through 05-09-2014",

}

Guillo Sansano, E, Roscoe, A, Jones, C & Burt, G 2014, A new control method for the power interface in power hardware-in-the-loop simulation to compensate for the time delay. in 2014 49th International Universities Power Engineering Conference (UPEC). IEEE, 49th International Universities Power Engineering Conference, UPEC 2014, Cluj-Napoca, Romania, 2/09/14. https://doi.org/10.1109/UPEC.2014.6934618

TY - GEN

T1 - A new control method for the power interface in power hardware-in-the-loop simulation to compensate for the time delay

AU - Guillo Sansano, Efren

AU - Roscoe, Andrew

AU - Jones, Catherine

AU - Burt, Graeme

PY - 2014/9

Y1 - 2014/9

N2 - In an attempt to create a new control method for the power interface in PHIL simulations, a simulated PHIL simulation is carried out where the simulation and hardware part are modelled in MATLAB/Simulink along with the new control method. This power interface control is proposed to achieve high accuracy in PHIL simulation with closed-loop control for aerospace, marine or micro grid applications. Rather than analyzing the Real Time Simulator (RTS) data and controlling the interface using time-domain resonant controllers, the RTS data will be analyzed and controlled at the interface in the frequency domain, on a harmonic-by-harmonic and phase-by-phase basis. This should allow the RTS time delay to be compensated accurately, and removes the requirement to include additional components to compensate for the simulation delay into the simulated power system as it is not appropriate for power systems which have short transmission lines. This is extremely relevant for marine and micro grid scenarios where such inductive components may not be present.

AB - In an attempt to create a new control method for the power interface in PHIL simulations, a simulated PHIL simulation is carried out where the simulation and hardware part are modelled in MATLAB/Simulink along with the new control method. This power interface control is proposed to achieve high accuracy in PHIL simulation with closed-loop control for aerospace, marine or micro grid applications. Rather than analyzing the Real Time Simulator (RTS) data and controlling the interface using time-domain resonant controllers, the RTS data will be analyzed and controlled at the interface in the frequency domain, on a harmonic-by-harmonic and phase-by-phase basis. This should allow the RTS time delay to be compensated accurately, and removes the requirement to include additional components to compensate for the simulation delay into the simulated power system as it is not appropriate for power systems which have short transmission lines. This is extremely relevant for marine and micro grid scenarios where such inductive components may not be present.

KW - interface algorithm

KW - real-time systems

KW - simulation accuracy

KW - simulation time delay

UR - http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6917609

U2 - 10.1109/UPEC.2014.6934618

DO - 10.1109/UPEC.2014.6934618

M3 - Conference contribution book

SN - 978-1-4799-6556-4

BT - 2014 49th International Universities Power Engineering Conference (UPEC)

PB - IEEE

T2 - 49th International Universities Power Engineering Conference, UPEC 2014

Y2 - 2 September 2014 through 5 September 2014

ER -

A new control method for the power interface in power hardware-in-the-loop simulation to compensate for the time delay

Abstract

Conference

Keywords

UN SDGs

Access to Document

Other files and links

Fingerprint

Dynamic Power Systems Laboratory

Cite this

A new control method for the power interface in power hardware-in-the-loop simulation to compensate for the time delay

Abstract

Conference

Keywords

UN SDGs

Access to Document

Other files and links

Fingerprint

Equipment

Dynamic Power Systems Laboratory

Cite this