A low nonlinearity, missing-code free time-to-digital converter based on 28nm FPGAs with embedded bin-width calibrations

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Abstract

This paper presents a low nonlinearity, missing-code free, time-to-digital converter (TDC) implemented in a 28nm Field Programmable Gate Array (FPGA) device (Xilinx Virtex 7 XC7V690T) with novel direct bin-width calibrations. We combine the tuned tapped delay lines (TDLs) and a modified direct-histogram architecture to correct the non-uniformity originated from carry chains, and use a multi-phase sampling structure to minimize the skews of clock routes. Results of code density tests show that the proposed TDC has much better linearity performances than previously published TDCs. Moreover, our TDC does not generate missing codes. For a single TDL, the differential nonlinearity (DNL) is within [-0.38, 0.87] LSB (the least significant bit: 10.5 ps) with σDNL = 0.20 LSB, and the integral nonlinearity (INL) is within [-1.23, 1.02] LSB with σ INL = 0.50 LSB. Based on the modified direct-histogram architecture, a direct bin-width calibration method was implemented and verified in the FPGA. By implementing embedded bin-width calibrations, the histogram data of TDCs can be calibrated on the fly. After the calibration, the DNLpk-pk (peak-to-peak DNL) and INLpk-pk (peak-to-peak INL) can be reduced to 0.08LSB with σDNL = 0.01LSB and 0.13 LSB with σINL = 0.02LSB respectively.
LanguageEnglish
Pages1912 - 1921
Number of pages10
JournalIEEE Transactions on Instrumentation and Measurement
Volume66
Issue number7
Early online dateApr 2017
DOIs
Publication statusPublished - 1 Jul 2017

Fingerprint

Bins
converters
Field programmable gate arrays (FPGA)
nonlinearity
Calibration
histograms
Electric delay lines
field-programmable gate arrays
delay lines
Clocks
nonuniformity
clocks
linearity
Sampling
sampling
routes

Keywords

  • bin width
  • carry chains
  • field-programmable gate arrays
  • multi-phase clock
  • time-of-flight
  • time-to-digital converters
  • Virtex-7

Cite this

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title = "A low nonlinearity, missing-code free time-to-digital converter based on 28nm FPGAs with embedded bin-width calibrations",
abstract = "This paper presents a low nonlinearity, missing-code free, time-to-digital converter (TDC) implemented in a 28nm Field Programmable Gate Array (FPGA) device (Xilinx Virtex 7 XC7V690T) with novel direct bin-width calibrations. We combine the tuned tapped delay lines (TDLs) and a modified direct-histogram architecture to correct the non-uniformity originated from carry chains, and use a multi-phase sampling structure to minimize the skews of clock routes. Results of code density tests show that the proposed TDC has much better linearity performances than previously published TDCs. Moreover, our TDC does not generate missing codes. For a single TDL, the differential nonlinearity (DNL) is within [-0.38, 0.87] LSB (the least significant bit: 10.5 ps) with σDNL = 0.20 LSB, and the integral nonlinearity (INL) is within [-1.23, 1.02] LSB with σ INL = 0.50 LSB. Based on the modified direct-histogram architecture, a direct bin-width calibration method was implemented and verified in the FPGA. By implementing embedded bin-width calibrations, the histogram data of TDCs can be calibrated on the fly. After the calibration, the DNLpk-pk (peak-to-peak DNL) and INLpk-pk (peak-to-peak INL) can be reduced to 0.08LSB with σDNL = 0.01LSB and 0.13 LSB with σINL = 0.02LSB respectively.",
keywords = "bin width, carry chains, field-programmable gate arrays, multi-phase clock, time-of-flight, time-to-digital converters, Virtex-7",
author = "Haochang Chen and Yongliang Zhang and Li, {David Day-Uei}",
note = "{\circledC} 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.",
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AU - Chen, Haochang

AU - Zhang, Yongliang

AU - Li, David Day-Uei

N1 - © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

PY - 2017/7/1

Y1 - 2017/7/1

N2 - This paper presents a low nonlinearity, missing-code free, time-to-digital converter (TDC) implemented in a 28nm Field Programmable Gate Array (FPGA) device (Xilinx Virtex 7 XC7V690T) with novel direct bin-width calibrations. We combine the tuned tapped delay lines (TDLs) and a modified direct-histogram architecture to correct the non-uniformity originated from carry chains, and use a multi-phase sampling structure to minimize the skews of clock routes. Results of code density tests show that the proposed TDC has much better linearity performances than previously published TDCs. Moreover, our TDC does not generate missing codes. For a single TDL, the differential nonlinearity (DNL) is within [-0.38, 0.87] LSB (the least significant bit: 10.5 ps) with σDNL = 0.20 LSB, and the integral nonlinearity (INL) is within [-1.23, 1.02] LSB with σ INL = 0.50 LSB. Based on the modified direct-histogram architecture, a direct bin-width calibration method was implemented and verified in the FPGA. By implementing embedded bin-width calibrations, the histogram data of TDCs can be calibrated on the fly. After the calibration, the DNLpk-pk (peak-to-peak DNL) and INLpk-pk (peak-to-peak INL) can be reduced to 0.08LSB with σDNL = 0.01LSB and 0.13 LSB with σINL = 0.02LSB respectively.

AB - This paper presents a low nonlinearity, missing-code free, time-to-digital converter (TDC) implemented in a 28nm Field Programmable Gate Array (FPGA) device (Xilinx Virtex 7 XC7V690T) with novel direct bin-width calibrations. We combine the tuned tapped delay lines (TDLs) and a modified direct-histogram architecture to correct the non-uniformity originated from carry chains, and use a multi-phase sampling structure to minimize the skews of clock routes. Results of code density tests show that the proposed TDC has much better linearity performances than previously published TDCs. Moreover, our TDC does not generate missing codes. For a single TDL, the differential nonlinearity (DNL) is within [-0.38, 0.87] LSB (the least significant bit: 10.5 ps) with σDNL = 0.20 LSB, and the integral nonlinearity (INL) is within [-1.23, 1.02] LSB with σ INL = 0.50 LSB. Based on the modified direct-histogram architecture, a direct bin-width calibration method was implemented and verified in the FPGA. By implementing embedded bin-width calibrations, the histogram data of TDCs can be calibrated on the fly. After the calibration, the DNLpk-pk (peak-to-peak DNL) and INLpk-pk (peak-to-peak INL) can be reduced to 0.08LSB with σDNL = 0.01LSB and 0.13 LSB with σINL = 0.02LSB respectively.

KW - bin width

KW - carry chains

KW - field-programmable gate arrays

KW - multi-phase clock

KW - time-of-flight

KW - time-to-digital converters

KW - Virtex-7

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DO - 10.1109/TIM.2017.2663498

M3 - Article

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EP - 1921

JO - IEEE Transactions on Instrumentation and Measurement

T2 - IEEE Transactions on Instrumentation and Measurement

JF - IEEE Transactions on Instrumentation and Measurement

SN - 0018-9456

IS - 7

ER -