A key agile 17.4 Gbit/sec Camellia implementation

Daniel Denning; James Irvine; Malachy Devlin; Jurgen Becker; Marco Platzner; Serge Vernalde

A key agile 17.4 Gbit/sec Camellia implementation

Daniel Denning, James Irvine, Malachy Devlin, Jurgen Becker (Editor), Marco Platzner (Editor), Serge Vernalde (Editor)

Electronic And Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Chapter

4 Citations (Scopus)

Abstract

In this paper we discuss several key agile Camellia implementations. The New European Schemes for Signatures, Integrity, and Encryption (NESSIE) selected Camellia in its portfolio of strong cryptographic algorithms for protecting the information society. In order for an encryption core to be key agile it must be able to accept new secret keys as well as data on every clock cycle. We discuss the design and implementation of the Camellia algorithm for a FPGA. We obtain a throughput of 17.4 Gbit/sec when running on a Virtex-II FPGA device.

Original language	English
Title of host publication	Field-Programmable Logic and Applications (FPL) 14th International Conference Proceedings
Place of Publication	Berlin-Heidelberg
Publisher	Springer-Verlag
Pages	546-554
Number of pages	8
Volume	3203
ISBN (Print)	3-540-22989-2
Publication status	Published - 2004

Publication series

Name	Lecture Notes in Computer Science
Publisher	Springer-Verlag

Keywords

key agile Camellia implementation
NESSIE
cryptographic algorithms
secret keys
Camellia algorithm

Cite this

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title = "A key agile 17.4 Gbit/sec Camellia implementation",

abstract = "In this paper we discuss several key agile Camellia implementations. The New European Schemes for Signatures, Integrity, and Encryption (NESSIE) selected Camellia in its portfolio of strong cryptographic algorithms for protecting the information society. In order for an encryption core to be key agile it must be able to accept new secret keys as well as data on every clock cycle. We discuss the design and implementation of the Camellia algorithm for a FPGA. We obtain a throughput of 17.4 Gbit/sec when running on a Virtex-II FPGA device.",

keywords = "key agile Camellia implementation, NESSIE, cryptographic algorithms, secret keys, Camellia algorithm",

author = "Daniel Denning and James Irvine and Malachy Devlin and Jurgen Becker and Marco Platzner and Serge Vernalde",

note = "Paper presented at the 14th international conference on Field Programmable Logic and Applications (FPL), Belgium, 2004.",

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A key agile 17.4 Gbit/sec Camellia implementation. / Denning, Daniel; Irvine, James; Devlin, Malachy et al.

Field-Programmable Logic and Applications (FPL) 14th International Conference Proceedings. Vol. 3203 Berlin-Heidelberg : Springer-Verlag, 2004. p. 546-554 (Lecture Notes in Computer Science).

Research output: Chapter in Book/Report/Conference proceeding › Chapter

TY - CHAP

T1 - A key agile 17.4 Gbit/sec Camellia implementation

AU - Denning, Daniel

AU - Irvine, James

AU - Devlin, Malachy

A2 - Becker, Jurgen

A2 - Platzner, Marco

A2 - Vernalde, Serge

N1 - Paper presented at the 14th international conference on Field Programmable Logic and Applications (FPL), Belgium, 2004.

PY - 2004

Y1 - 2004

N2 - In this paper we discuss several key agile Camellia implementations. The New European Schemes for Signatures, Integrity, and Encryption (NESSIE) selected Camellia in its portfolio of strong cryptographic algorithms for protecting the information society. In order for an encryption core to be key agile it must be able to accept new secret keys as well as data on every clock cycle. We discuss the design and implementation of the Camellia algorithm for a FPGA. We obtain a throughput of 17.4 Gbit/sec when running on a Virtex-II FPGA device.

AB - In this paper we discuss several key agile Camellia implementations. The New European Schemes for Signatures, Integrity, and Encryption (NESSIE) selected Camellia in its portfolio of strong cryptographic algorithms for protecting the information society. In order for an encryption core to be key agile it must be able to accept new secret keys as well as data on every clock cycle. We discuss the design and implementation of the Camellia algorithm for a FPGA. We obtain a throughput of 17.4 Gbit/sec when running on a Virtex-II FPGA device.

KW - key agile Camellia implementation

KW - NESSIE

KW - cryptographic algorithms

KW - secret keys

KW - Camellia algorithm

UR - http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2004.html

M3 - Chapter

SN - 3-540-22989-2

VL - 3203

T3 - Lecture Notes in Computer Science

SP - 546

EP - 554

BT - Field-Programmable Logic and Applications (FPL) 14th International Conference Proceedings

PB - Springer-Verlag

CY - Berlin-Heidelberg

ER -

A key agile 17.4 Gbit/sec Camellia implementation

Abstract

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Keywords

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