A key agile 17.4 Gbit/sec Camellia implementation

Daniel Denning, James Irvine, Malachy Devlin, Jurgen Becker (Editor), Marco Platzner (Editor), Serge Vernalde (Editor)

Research output: Chapter in Book/Report/Conference proceedingChapter

3 Citations (Scopus)

Abstract

In this paper we discuss several key agile Camellia implementations. The New European Schemes for Signatures, Integrity, and Encryption (NESSIE) selected Camellia in its portfolio of strong cryptographic algorithms for protecting the information society. In order for an encryption core to be key agile it must be able to accept new secret keys as well as data on every clock cycle. We discuss the design and implementation of the Camellia algorithm for a FPGA. We obtain a throughput of 17.4 Gbit/sec when running on a Virtex-II FPGA device.
Original languageEnglish
Title of host publicationField-Programmable Logic and Applications (FPL) 14th International Conference Proceedings
Place of PublicationBerlin-Heidelberg
PublisherSpringer-Verlag
Pages546-554
Number of pages8
Volume3203
ISBN (Print)3-540-22989-2
Publication statusPublished - 2004

Publication series

NameLecture Notes in Computer Science
PublisherSpringer-Verlag

Keywords

  • key agile Camellia implementation
  • NESSIE
  • cryptographic algorithms
  • secret keys
  • Camellia algorithm

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