A design flow for partially reconfigurable hardware

I. Robinson, J. Irvine

Research output: Contribution to journalArticle

25 Citations (Scopus)

Abstract

This paper presents a top-down designer-driven design flow for creating hardware that exploits partial run-time reconfiguration. Computer-aided design (CAD) tools are presented, which complement conventional FPGA design environments to enable the specification, simulation (both functional and timing), synthesis, automatic placement and routing, partial configuration generation and control of partially reconfigurable designs. Collectively these tools constitute the dynamic circuit switching CAD framework. A partially reconfigurable Viterbi decoder design is presented to demonstrate the design flow and illustrate possible power consumption reductions and performance improvements through the exploitation of partial reconfiguration.
LanguageEnglish
Pages257-283
Number of pages26
JournalACM Transactions in Embedded Computing Systems
Volume3
Issue number2
DOIs
Publication statusPublished - 2004

Fingerprint

Reconfigurable hardware
Computer aided design
Switching circuits
Computer hardware
Field programmable gate arrays (FPGA)
Electric power utilization
Specifications

Keywords

  • FPGA
  • Viterbi decoder
  • configuration control
  • power estimation
  • electrical systems
  • control systems
  • computer aided engineering

Cite this

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A design flow for partially reconfigurable hardware. / Robinson, I.; Irvine, J.

In: ACM Transactions in Embedded Computing Systems, Vol. 3, No. 2, 2004, p. 257-283.

Research output: Contribution to journalArticle

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