A comprehensive analysis on data hazard for RISC32 5-Stage pipeline processor

Wei Pau Kiat, Kai Ming Mok, Wai Kong Lee, Hock Guan Goh, Ivan Andonovic

Research output: Chapter in Book/Report/Conference proceedingConference contribution book

2 Citations (Scopus)

Abstract

This paper describes the verification plan on data hazard detection and handling for a 32-bit MIPS ISA (Microprocessor without Interlocked Pipeline Stages Instruction Set Architecture) compatible 5-stage pipeline processor, RISC32. Our work can be used as a reference for RISC32 processor developers to identify and resolve every possible data hazard that might arise during execution phase within the range of the basic MIPS core instruction set. The techniques used to resolve data hazard in this paper are data forwarding and pipeline stages stalling. When data hazard arises, it is first resolve by using data forwarding. If the problem persists, we use pipeline stages stalling then only follow by another data forwarding to resolve the data hazard. This combination will reduce the impact of data hazard on the processor throughput, instead of only using the pipeline stages stalling. This paper delivers a comprehensive analysis and the development of the data hazard resolving blocks that are able to resolve data hazard arises.

LanguageEnglish
Title of host publicationProceedings - 31st IEEE International Conference on Advanced Information Networking and Applications Workshops, WAINA 2017
Place of PublicationPiscataway, N.J.
PublisherIEEE
Pages154-159
Number of pages6
ISBN (Print)9781509062300
DOIs
Publication statusPublished - 16 May 2017
Event31st IEEE International Conference on Advanced Information Networking and Applications Workshops, WAINA 2017 - Taipei, Taiwan, Province of China
Duration: 27 Mar 201729 Mar 2017

Conference

Conference31st IEEE International Conference on Advanced Information Networking and Applications Workshops, WAINA 2017
CountryTaiwan, Province of China
CityTaipei
Period27/03/1729/03/17

Fingerprint

Hazards
Pipelines
Microprocessor chips
Throughput

Keywords

  • data forwarding
  • data hazard
  • interlock pipeline stages
  • MIPS
  • pipeline

Cite this

Kiat, W. P., Mok, K. M., Lee, W. K., Goh, H. G., & Andonovic, I. (2017). A comprehensive analysis on data hazard for RISC32 5-Stage pipeline processor. In Proceedings - 31st IEEE International Conference on Advanced Information Networking and Applications Workshops, WAINA 2017 (pp. 154-159). Piscataway, N.J.: IEEE. https://doi.org/10.1109/WAINA.2017.20
Kiat, Wei Pau ; Mok, Kai Ming ; Lee, Wai Kong ; Goh, Hock Guan ; Andonovic, Ivan. / A comprehensive analysis on data hazard for RISC32 5-Stage pipeline processor. Proceedings - 31st IEEE International Conference on Advanced Information Networking and Applications Workshops, WAINA 2017. Piscataway, N.J. : IEEE, 2017. pp. 154-159
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abstract = "This paper describes the verification plan on data hazard detection and handling for a 32-bit MIPS ISA (Microprocessor without Interlocked Pipeline Stages Instruction Set Architecture) compatible 5-stage pipeline processor, RISC32. Our work can be used as a reference for RISC32 processor developers to identify and resolve every possible data hazard that might arise during execution phase within the range of the basic MIPS core instruction set. The techniques used to resolve data hazard in this paper are data forwarding and pipeline stages stalling. When data hazard arises, it is first resolve by using data forwarding. If the problem persists, we use pipeline stages stalling then only follow by another data forwarding to resolve the data hazard. This combination will reduce the impact of data hazard on the processor throughput, instead of only using the pipeline stages stalling. This paper delivers a comprehensive analysis and the development of the data hazard resolving blocks that are able to resolve data hazard arises.",
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Kiat, WP, Mok, KM, Lee, WK, Goh, HG & Andonovic, I 2017, A comprehensive analysis on data hazard for RISC32 5-Stage pipeline processor. in Proceedings - 31st IEEE International Conference on Advanced Information Networking and Applications Workshops, WAINA 2017. IEEE, Piscataway, N.J., pp. 154-159, 31st IEEE International Conference on Advanced Information Networking and Applications Workshops, WAINA 2017, Taipei, Taiwan, Province of China, 27/03/17. https://doi.org/10.1109/WAINA.2017.20

A comprehensive analysis on data hazard for RISC32 5-Stage pipeline processor. / Kiat, Wei Pau; Mok, Kai Ming; Lee, Wai Kong; Goh, Hock Guan; Andonovic, Ivan.

Proceedings - 31st IEEE International Conference on Advanced Information Networking and Applications Workshops, WAINA 2017. Piscataway, N.J. : IEEE, 2017. p. 154-159.

Research output: Chapter in Book/Report/Conference proceedingConference contribution book

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Kiat WP, Mok KM, Lee WK, Goh HG, Andonovic I. A comprehensive analysis on data hazard for RISC32 5-Stage pipeline processor. In Proceedings - 31st IEEE International Conference on Advanced Information Networking and Applications Workshops, WAINA 2017. Piscataway, N.J.: IEEE. 2017. p. 154-159 https://doi.org/10.1109/WAINA.2017.20