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Abstract
Power system capacitor banks form critical components of reactive power support and filtering arrangements in high voltage direct current converter stations, such as those connecting electrical power networks with interconnectors, and with offshore wind resources which promise abundant renewable energy but are necessarily distant from centres of demand. Capacitor banks are typically configured in balanced arrangements, where standards require each unit to be measured individually at commissioning and positioned to best balance a neutral or bridge. Capacitor bank rack voltages are tiered but are shared among all units on each rack, which can test dielectrics: this paper presents simulation models to explore distributions of dielectric stress which can result from such arrangements. On a symmetrical rack configured with series-connected units, preliminary results suggest voltages (and therefore electric field stresses) are not evenly shared throughout units in the bank, as: each unit has its own uneven voltage distribution; and rack voltages common to all supported units subject those furthest from a rack tie connection to greater stress than those positioned centrally. Where dielectrics throughout a bank are similar, disproportionate stresses suggest incipient faults and eventual insulation breakdown are more probable for certain unit positions, such as corner units and those at higher voltage. An improved understanding of how unit position affects failure probability could help detect faults, corroborate failure locations detected with reactance techniques, or otherwise direct initial searches for degraded units.
Original language | English |
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Title of host publication | 2020 IEEE Electrical Insulation Conference (EIC) |
Place of Publication | Piscataway, NJ |
Publisher | IEEE |
Pages | 494-497 |
Number of pages | 4 |
ISBN (Electronic) | 9781728154855 |
ISBN (Print) | 9781728154862 |
DOIs | |
Publication status | Published - 5 Aug 2020 |
Event | 38th IEEE Electrical Insualtion Conference 2020 - Duration: 22 Jun 2020 → 3 Jul 2020 https://ieee-eic.org/ |
Conference
Conference | 38th IEEE Electrical Insualtion Conference 2020 |
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Abbreviated title | IEEE EIC 2020 |
Period | 22/06/20 → 3/07/20 |
Other | Virtual conference |
Internet address |
Keywords
- capacitor
- dielectrics
- high voltage
- simulation
Fingerprint
Dive into the research topics of 'A capacitor bank simulation model'. Together they form a unique fingerprint.Projects
- 1 Finished
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EPSRC Centre for Doctoral Training in Future Power Networks and Smart Grids | MacKinnon, Calum
Stewart, B. (Principal Investigator), McArthur, S. (Co-investigator) & MacKinnon, C. (Research Co-investigator)
EPSRC (Engineering and Physical Sciences Research Council)
1/10/15 → 14/03/22
Project: Research Studentship - Internally Allocated
Datasets
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Capacitor Unit Model File
Mackinnon, C. (Creator) & Stewart, B. (Supervisor), University of Strathclyde, 28 Sept 2021
DOI: 10.15129/a03a8415-43c0-4e19-9fee-748b67f5c0e1
Dataset
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Thermal profiles of high-voltage capacitor units
Mackinnon, C. J. & Stewart, B. G., 20 Oct 2019. 4 p.Research output: Contribution to conference › Paper › peer-review
Open AccessFile1 Citation (Scopus)91 Downloads (Pure) -
Regions of electrical stress in high voltage capacitor units
Mackinnon, C. & Stewart, B. G., 24 Sept 2019. 7 p.Research output: Contribution to conference › Paper › peer-review
Open AccessFile -
A high voltage capacitor element model
Mackinnon, C. J. & Stewart, B. G., 16 Jun 2019. 4 p.Research output: Contribution to conference › Paper › peer-review
Open AccessFile