A 1V 10-bit 400MS/s current steering D/A converter in 90-nm CMOS

Chueh-Hao Yu; Wen-Hui Chen; Day-Uei Li; Wan-Ju Huang

doi:10.1109/VDAT.2007.373232

A 1V 10-bit 400MS/s current steering D/A converter in 90-nm CMOS

Chueh-Hao Yu, Wen-Hui Chen, Day-Uei Li, Wan-Ju Huang

Strathclyde Institute Of Pharmacy And Biomedical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution book

6 Citations (Scopus)

Abstract

This paper presents the design of a 90 nm CMOS 1 V 10-bit 400MS/s digital-to-analog converter. Current-steering architecture segmented into 6 MSB unary and 4 LSB binary-weighted cells is employed for high-speed operations. The low voltage design with a large differential full-scale output voltage 0.5 Vpp is presented. The post-layout simulation results show that the SFDR and ENOB are 64.4 dB and 9.36 bit respectively with a full-scale 10.15 MHz input at 400 MS/s. This chip operates at a 1 V supply for the DAC core and 2.5 V for I/O interface and is fabricated in a 90 nm CMOS technology. Its active area is 0.51 x 0.55 mm2.

Original language	English
Title of host publication	International Symposium on VLSI Design, Automation and Test, 2007
Place of Publication	Piscataway
Publisher	IEEE
Number of pages	4
ISBN (Print)	1424405823
DOIs	https://doi.org/10.1109/VDAT.2007.373232
Publication status	Published - 18 Jun 2007

Keywords

decodong
latches
impedance
CMOS technology
digital circuits
low voltage
clocks
driver circuits
switching circuits
wireless communication

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10.1109/VDAT.2007.373232

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@inproceedings{5dad15ee983941b4af69f8a0a9b0af33,

title = "A 1V 10-bit 400MS/s current steering D/A converter in 90-nm CMOS",

abstract = "This paper presents the design of a 90 nm CMOS 1 V 10-bit 400MS/s digital-to-analog converter. Current-steering architecture segmented into 6 MSB unary and 4 LSB binary-weighted cells is employed for high-speed operations. The low voltage design with a large differential full-scale output voltage 0.5 Vpp is presented. The post-layout simulation results show that the SFDR and ENOB are 64.4 dB and 9.36 bit respectively with a full-scale 10.15 MHz input at 400 MS/s. This chip operates at a 1 V supply for the DAC core and 2.5 V for I/O interface and is fabricated in a 90 nm CMOS technology. Its active area is 0.51 x 0.55 mm2.",

keywords = "decodong, latches, impedance, CMOS technology, digital circuits, low voltage, clocks, driver circuits, switching circuits, wireless communication",

author = "Chueh-Hao Yu and Wen-Hui Chen and Day-Uei Li and Wan-Ju Huang",

year = "2007",

month = jun,

day = "18",

doi = "10.1109/VDAT.2007.373232",

language = "English",

isbn = "1424405823",

booktitle = "International Symposium on VLSI Design, Automation and Test, 2007",

publisher = "IEEE",

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TY - GEN

T1 - A 1V 10-bit 400MS/s current steering D/A converter in 90-nm CMOS

AU - Yu, Chueh-Hao

AU - Chen, Wen-Hui

AU - Li, Day-Uei

AU - Huang, Wan-Ju

PY - 2007/6/18

Y1 - 2007/6/18

N2 - This paper presents the design of a 90 nm CMOS 1 V 10-bit 400MS/s digital-to-analog converter. Current-steering architecture segmented into 6 MSB unary and 4 LSB binary-weighted cells is employed for high-speed operations. The low voltage design with a large differential full-scale output voltage 0.5 Vpp is presented. The post-layout simulation results show that the SFDR and ENOB are 64.4 dB and 9.36 bit respectively with a full-scale 10.15 MHz input at 400 MS/s. This chip operates at a 1 V supply for the DAC core and 2.5 V for I/O interface and is fabricated in a 90 nm CMOS technology. Its active area is 0.51 x 0.55 mm2.

AB - This paper presents the design of a 90 nm CMOS 1 V 10-bit 400MS/s digital-to-analog converter. Current-steering architecture segmented into 6 MSB unary and 4 LSB binary-weighted cells is employed for high-speed operations. The low voltage design with a large differential full-scale output voltage 0.5 Vpp is presented. The post-layout simulation results show that the SFDR and ENOB are 64.4 dB and 9.36 bit respectively with a full-scale 10.15 MHz input at 400 MS/s. This chip operates at a 1 V supply for the DAC core and 2.5 V for I/O interface and is fabricated in a 90 nm CMOS technology. Its active area is 0.51 x 0.55 mm2.

KW - decodong

KW - latches

KW - impedance

KW - CMOS technology

KW - digital circuits

KW - low voltage

KW - clocks

KW - driver circuits

KW - switching circuits

KW - wireless communication

U2 - 10.1109/VDAT.2007.373232

DO - 10.1109/VDAT.2007.373232

M3 - Conference contribution book

SN - 1424405823

BT - International Symposium on VLSI Design, Automation and Test, 2007

PB - IEEE

CY - Piscataway

ER -

A 1V 10-bit 400MS/s current steering D/A converter in 90-nm CMOS

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Keywords

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