A 1V 10-bit 400MS/s current steering D/A converter in 90-nm CMOS

Chueh-Hao Yu, Wen-Hui Chen, Day-Uei Li, Wan-Ju Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution book

4 Citations (Scopus)

Abstract

This paper presents the design of a 90 nm CMOS 1 V 10-bit 400MS/s digital-to-analog converter. Current-steering architecture segmented into 6 MSB unary and 4 LSB binary-weighted cells is employed for high-speed operations. The low voltage design with a large differential full-scale output voltage 0.5 Vpp is presented. The post-layout simulation results show that the SFDR and ENOB are 64.4 dB and 9.36 bit respectively with a full-scale 10.15 MHz input at 400 MS/s. This chip operates at a 1 V supply for the DAC core and 2.5 V for I/O interface and is fabricated in a 90 nm CMOS technology. Its active area is 0.51 x 0.55 mm2.
Original languageEnglish
Title of host publicationInternational Symposium on VLSI Design, Automation and Test, 2007
Place of PublicationPiscataway
PublisherIEEE
Number of pages4
ISBN (Print)1424405823
DOIs
Publication statusPublished - 18 Jun 2007

Keywords

  • decodong
  • latches
  • impedance
  • CMOS technology
  • digital circuits
  • low voltage
  • clocks
  • driver circuits
  • switching circuits
  • wireless communication

Fingerprint Dive into the research topics of 'A 1V 10-bit 400MS/s current steering D/A converter in 90-nm CMOS'. Together they form a unique fingerprint.

  • Cite this

    Yu, C-H., Chen, W-H., Li, D-U., & Huang, W-J. (2007). A 1V 10-bit 400MS/s current steering D/A converter in 90-nm CMOS. In International Symposium on VLSI Design, Automation and Test, 2007 Piscataway: IEEE. https://doi.org/10.1109/VDAT.2007.373232