A 192 x 128 time correlated single photon counting imager in 40nm CMOS technology

Robert K. Henderson, Nick Johnston, Haochang Chen, David Day-Uei Li, Graham Hungerford, Richard Hirsch, Philip Yip, David McLoskey, David Birch

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Abstract

A 192 x 128 pixel single photon avalanche diode (SPAD) time-resolved single photon counting (TCPSC) image sensor is implemented in STMicroelectronics 40nm CMOS technology. The 13 % fill-factor, 18.4 x 9.2 mm pixel contains a 33 ps resolution, 135 ns full-scale, 12-bit time to digital converter (TDC) with 0.9 LSB differential and 8.7 LSB integral nonlinearity (DNL/INL). The sensor achieves a mean 219 ps fullwidth half maximum (FWHM) impulse response function (IRF) and a 5 mW core power consumption and is operable at up to 18.6 kfps. Cylindrical microlenses with a concentration factor of 3.15 increase the fill-factor to 41%. The median dark count rate (DCR) is 25 Hz at 1.5 V excess bias. Fluorescence lifetime imaging (FLIM) results are presented.
Original languageEnglish
Title of host publication44th European Solid-State Circuits Conference (ESSCIRC) 2018
Place of PublicationPiscataway, NJ
PublisherIEEE
Number of pages4
Publication statusPublished - 4 Sep 2018
Event44th European Solid-State Circuits Conference - Dresden, Germany
Duration: 3 Sep 20186 Sep 2018

Conference

Conference44th European Solid-State Circuits Conference
CountryGermany
CityDresden
Period3/09/186/09/18

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Keywords

  • single photon avalanche diode
  • photon counting

Cite this

Henderson, R. K., Johnston, N., Chen, H., Li, D. D-U., Hungerford, G., Hirsch, R., ... Birch, D. (2018). A 192 x 128 time correlated single photon counting imager in 40nm CMOS technology. In 44th European Solid-State Circuits Conference (ESSCIRC) 2018 Piscataway, NJ: IEEE.