Personal profile

Personal Statement

I graduated with an undergraduate degree in Electronic and Electrical Engineering at the University of Strathclyde in 2015 with a First Class Honours. In 2023, I completed my PhD studies at the University on The Efficient Implementation of the Line Hough Transform for Embedded Vision Systems. My key research interests include efficiently implementing wireless communication systems and computer vision applications on Field Programmable Gate Arrays (FPGAs) and System-on-Chip (SoC) technologies.

I am currently employed as a Research Associate at the University, conducting research and knowledge exchange activities around Software-Defined Radio (SDR), primarily targeting the AMD Radio Frequency System-on-Chip (RFSoC) and related devices and design tools. My responsibilities include developing RFSoC designs, prototypes, and tutorials to progress state-of-the-art SDR implementation and contemporary research into RFSoC applications. Additionally, I frequently engage with industry collaborators, supervise researchers and students, and assist with teaching in the University on FPGA and SoC design.

Over the last six years, I have published and presented at several international conferences, presenting my research on spectrum monitoring with the AMD RFSoC. This work includes the RFSoC Spectrum Analyser, a tool capable of simultaneously inspecting the frequency spectra of multiple wideband radio channels. In addition, I have participated in various tutorial events on RFSoC-PYNQ, an open-source software framework developed by AMD, commonly known as Python Productivity on Zynq. I have co-published a journal paper in IEEE Access on RFSoC-PYNQ, highlighting its introspection, visualisation, and control capabilities towards FPGA and RFSoC designs.

I co-authored the technical book Exploring Zynq MPSoC with PYNQ and Machine Learning Applications, published in 2019. This book described the architecture, features, and capabilities of the Zynq MPSoC and was a valuable guide for those getting started with the device. In 2023, I recently edited and co-authored a new technical book named Software Defined Radio with Zynq UltraScale+ RFSoC. This book introduced the AMD RFSoC, providing rich chapters describing its architecture and fundamental operating principles. The technical book also contains 32 practical exercises for engineers and researchers to become familiar with the RFSoC platform and its theory of operation.

Previously, I have undertaken internships and positions in industry. In 2018, I was a Signal Processing Intern at MathWorks, where I worked on the vision Zynq support package and designed SoC architectures using MathWorks` workflows. During the pandemic from 2020 to 2021, I worked remotely with Xilinx as a Research Lab Intern. In this internship, I applied my Digital Signal Processing (DSP) and FPGA design expertise to develop systems for the RFSoC. In 2022, I worked part-time as a Senior FPGA Engineer at the University spin-out Neutral Wireless. In this role, I consulted with clients to obtain requirements specifications and worked alongside a team to design and develop SDR applications on FPGA and SoC devices.

Expertise related to UN Sustainable Development Goals

In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This person’s work contributes towards the following SDG(s):

  • SDG 9 - Industry, Innovation, and Infrastructure
  • SDG 11 - Sustainable Cities and Communities

Education/Academic qualification

Doctor of Philosophy, On the Efficient Implementation of the Line Hough Transform for Embedded Vision Systems, University Of Strathclyde

1 Oct 201511 Aug 2023

Award Date: 31 Oct 2023

Postgraduate Certificate in Researcher Professional Development, University Of Strathclyde

1 Oct 201511 Aug 2023

Award Date: 31 Oct 2023

Bachelor of Engineering, Electronic and Electrical Engineering, University Of Strathclyde

Sept 2011Jun 2015

Award Date: 10 Jun 2015

External positions

Senior FPGA Engineer, Neutral Wireless Ltd

Nov 2021Oct 2022

Research Lab Intern, Xilinx Inc

Oct 2020Apr 2021

Signal Processing Intern, The Mathworks Ltd

Sept 2018Dec 2018


  • SoC
  • FPGA
  • Image Processing
  • Zynq
  • Video Processing
  • RFSoC
  • DSP
  • Wireless Communications


Dive into the research topics where David Northcote is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
  • 1 Similar Profiles

Collaborations and top research areas from the last five years

Recent external collaboration on country/territory level. Dive into details by clicking on the dots or