High-Level synthesis of hardware accelerated 3D image segmentation based on Otsu's method

Dataset used to create hardware implementation of 3D image segmentation algorithm utilising a mean filter and thresholds generated using Otsu's method. The implementation was created using Xilinx' SDSoC development environment software and tested on hardware using the ZedBoard. This data formed the basis of a conference paper presented at the 26th International Conference on Field Programmable Logic and Applications (FPL 2016). Further details of the data contained in this dataset are given in the README.txt file.